Several one transistor (1T)-capacitorless cells that store charge in the body of a silicon-on-insulator (SOI) metal oxide semiconductor field effect transistor (MOSFET) are known in the art. Both the Fazan cell (See, for example, IEEE Electron Device Letters, Vol. 23, No. 2, February 2002) and the Toshiba cell (See, for example, IEEE Journal of Solid-State Circuits, Vol. 37, No. 11, November 2002) are examples of such cells.
The Toshiba cell improves upon the Fazan cell by enhancing the body capacitance with a conducting plate coupled to the sidewall of the SOI layer through a dielectric. The plate is connected to the substrate through the buried oxide (BOX) of the SOI. Although the Toshiba cell results in enhanced body charge, and improves the distinction between a “0” (minimum quantity of body majority carriers) and a “1” (maximum accumulation of majority carriers), due to alignment tolerances the amount of overlap between the plate-bitline diffusion and plate-source diffusion varies randomly from cell to cell, and across the chip. This random variation in overlap adds a parasitic capacitance that increases the average bitline capacitance. This increased bitline capacitance results in a combination of slower performance, increased chip area (because larger drivers are required to compensate for the larger parasitic capacitance), and increased dynamic power dissipation.
In view of the above drawbacks with prior art 1T-capacitorless cells, there is a need to provide such as cell that avoids excessive overlap of the body capacitor plate with the bitline diffusion.